When measuring items, scales of different degrees of precision can be used. For example, one can measure things on a scale with three division marks (zero to two), or on a scale of the same magnitude with ten division marks (zero to nine). Scales with more divisions are of higher precision than scales with fewer divisions. On a computer, because of processing and storage limitations, numerical values are also represented with varying degrees of precision. For example, one can use two bits (a scale of zero to three) to represent a numerical value or use five bits (a scale of zero to thirty-one) to represent the same numerical value. The number of bits used to represent a numerical value is generally referred to as the "bit depth."
While it saves storage space for numerical data to be represented with low bit depth, it is sometimes useful to increase the precision of the stored data for processing and other purposes. For example, it might be efficient to have video data stored as 4-bit pixel values and then increase the precision to 8 bits for display. In these scenarios, one would be required to map the full range of the original lower scale to the full range of the new higher scale. In the previous example, a zero in the 4-bit value will map a zero in the 9-bit value whereas a 15 will map to a 255.
This bit-depth increase can be formally characterized as follows. For data with a bit-depth of q, the level L.sub.i will be from the range EQU L.sub.i .epsilon.{0,1,2, . . . ,2.sup.q -1}.
This input data is to have their bit-depth increased to m to yield output levels of L.sub.o from the range EQU L.sub.o .epsilon.{0, . . . ,2.sup.m -1}.
This can be achieved by performing a multiplication by an ideal gain, ##EQU1## followed by rounding to the nearest integer: EQU L.sub.o =Round{G.times.L.sub.i }.
A number of techniques have been proposed for expanding the number of bits representing particular data. A conventional technique commonly used in computer graphics is to expand the number of bits by simply padding the originally received bits with additional zero-bits to represent the data. Using such a technique, zero-bits are appended to the received data bits to expand the bit length to the desired number of bits.
For example, if data represented by 3 bits is expanded to 8 bits using the above-described conventional technique, the number 7 which is represented by 3 one-bits, can be represented by 3 one-bits followed by 5 zero-bits in an expanded 8-bit representation.
As will be recognized by those skilled in the art, a 3-bit representation can be used to represent the numbers 0 to 7 while an 8-bit representation can be used to represent the numbers 0 to 255. Hence, a 3-bit representation of the number 7 would ideally be expanded into an 8-bit representation of the number 255. However, as shown in FIG. 1, by simply padding the original bits with 0 bits to form the 8-bit representation, the gain is less than ideal. Therefore, the padded data is an imprecise representation of the original data.
To obtain an exact solution, the number represented by the original data bits could be multiplied by the desired gain ratio. For example, in the bit-depth increase shown in FIG. 1, the desired gain ratio is 255/7. Accordingly, to precisely subject any number represented by the original 3 bits to bit-depth increase, the number can be up-multiplied by the gain ratio and this up-multiplied number will be represented by the 8 bits of the expanded data representation. However, this requires a multiplier and would therefore add to the processing overhead required to subject the original data to bit-depth increase. As will be recognized by those skilled in the art, multipliers can be quite expensive and are typically implemented in hardware. Further, since multiplying the number represented by the original 3 bits by the gain ratio will not necessarily result in an integer number, the result of the up-multiplying must be rounded to the nearest integer and hence the 8-bit representation is less than perfect. Thus, even more processing time and hardware expense may be required only to obtain a near perfect bit-depth increase.
FIG. 1 depicts a prior art bit-depth increaser which includes a 3-bit input register 110 having a set of three registers and an 8-bit output register 120 having a set of eight registers. The three registers of the input register 110 are hard wired to the three most significant bit registers in the output register 120 via connectors, e.g., wires 140. A padder 130 is hard wired via connectors 150 to the remaining registers, i.e., the five least significant bit registers of the output register 120. As will be recognized by those skilled in the art, the 3-bit input register 110 is capable of storing numbers 0-7 while the 8-bit output register 120 is capable of storing numbers 0-255. As depicted, the input register 110 stores input data representing the numeric 5. To bit-depth increase the input data to an expanded 8 bit representation, the input data is mapped and transmitted from input register 110 to the output register 120 via connectors 140 for storage as the 3 most significant bits in the noted sequence. The remaining registers of the output register 120 are padded by the padder 130 with zeros transmitted via the wires or connectors 150. The output register 120 outputs an imprecise approximation of the numeric 5 in an 8-bit format as represented by the values in the eight registers of the output register 120.
As noted above, to improve the precision of the output signal, the bits stored in the input register could be up-multiplied by the precise gain factor and result stored in the output register using an 8-bit representation. As shown in FIG. 2, an input register 210 stores a 3-bit representation of input data. As indicated in FIG. 2, the stored bits in input register 210 represent the numeric 5. The stored information is transmitted from input register 210 to the multiplier 230 via the connector 250. The multiplier 230 up-multiplies the numeric 5 by the gain factor 255/7 to compute a corresponding 8-bit value which will more precisely bit-depth increase the 3-bit input data stored in the input register 210. As shown in FIG. 2, the result of this multiplication equals a non-integer number, i.e., 182.14, which is transmitted via connector 260 to a rounder 240. The number is then rounded to the nearest integer value, i.e., 182, and represented by the 8-bits stored in the output register 220. A more precise 8-bit representation of the 3 bit input data has thus been formed and can be output from output register 220 for use by, for example, an 8-bit processor.
FIGS. 3A-3C detail the bit-depth increase process as the data passes through the system of FIG. 2. FIG. 3A depicts the 3 input bits representing the numeric 5 which are stored in the input register 210 and transmitted to the multiplier 230 via the connector 250. FIG. 3B depicts the bit-depth increased signal as it is output from the multiplier 230 after having been subject to bit depth increase. As shown, the multiplier outputs eight integer bits 320A, which are transmitted via connectors 260 to the rounder 240, representing the numeric 182 and includes four fractional bits 320B representing the numeric 0.14. The rounder 240 rounds the received data to the nearest integer value. Accordingly, as shown in FIG. 3C, the 8-bit representation output from rounder 240 to the output register 220 via connector 270 represents a numeric value equalling 182. If, for example, the fractional bits had equalled more than 0.50, the numeric value represented in FIG. 3C would have been 183. Here again, it should be noted that the 8-bit data represented by the bits 330 is less than precise due to rounding error.
As discussed above, a significant expense is involved in implementing the multiplier 230 and rounder 240 shown in FIG. 2. Additionally, the multiplying and rounding increase the signal processing time to obtain an expanded signal. Thus, although the system depicted in FIG. 2 provides a more precise representation of the input data as compared to that shown in FIG. 1, the enhanced precision comes at a significant cost in terms of both system cost, hardware requirements, and processing time.